This disclosure generally relates to a non-volatile memory device and, more particularly, to a row selection circuit for applying wordline voltages based on each operation mode to wordlines of a selected block.
There are growing demands for electrically erasable and programmable semiconductor memory devices in a semiconductor memory device. In addition, such memory devices trend toward higher capacity and integration density. A NAND flash memory device is an example of a non-volatile memory device that can meet higher capacity and integration density without the need to refresh stored data. Since the NAND flash memory device continuously holds data even when a power supply is interrupted, it has widely been used in electronic apparatuses (e.g., portable terminals, handheld computers, cellular phones, digital cameras, etc.).
A conventional NAND flash memory device 10 is illustrated in FIG. 1.
Referring to FIG. 1, a NAND flash memory device includes a memory cell array 20, a row selection circuit (X-SEL) 40, and a sense and latch circuit 60. The memory cell array 20 has a plurality of cell strings (or NAND strings) 21 that are coupled to bitlines BL0-BLm, respectively. The cell string 21 of each column includes a string selection transistor SST serving as a first selection transistor, a ground selection transistor GST serving as a second selection transistor, and a plurality of EEPROM cells MCn (n=0-15) serially connected between the selection transistors SST and GST. The string selection transistor SST of each column has a drain coupled to a corresponding bitline and a gate coupled to a string selection line SSL. The ground selection transistor GST has a source coupled to a common source line CSL and a gate coupled to a ground selection line GSL. Flash EEPROM cells MC15-MC0 are serially connected between a source of the string selection transistor SST and a drain of the ground selection transistor GST. Further, the flash EEPROM cells MC15-MC0 are each coupled to their corresponding wordlines WL15-WL0.
A memory cell array 20 constitutes a memory block and is a so-called xe2x80x9cmatxe2x80x9d. Although only one memory block is illustrated in the figure, a number of memory blocks may be arranged with the same structure as shown in FIG. 1. In this case, the memory blocks are to share bitlines BL0-BLm.
The string selection line SSL, the wordlines WL0-WL15, and the ground selection line GSL are electrically connected to a row selection circuit 40. The row selection circuit 40 selects one of the wordlines WL0-WL15 according to address information, and applies wordline voltages based on each operation mode to a selected wordline and unselected wordlines. This will be explained in detail below. Bitlines BL0-BLm arranged through the memory cell array 20 are electrically connected to the sense and latch circuit 60. The sense and latch circuit 60 senses data from flash EEPROM cells of a selected wordline through the bitlines BL0-BLm in a read operation mode, and applies a power supply voltage or a ground voltage to the bitlines BL0-BLm based on data to be programmed in a program operation mode, respectively.
In a program operation mode, the row selection circuit 40 applies a program voltage Vpgm (e.g., 18V) to a selected wordline and applies a pass voltage Vpass (e.g., 10V) to unselected bitlines. In a read operation mode, the row selection circuit 40 applies a ground voltage GND to a selected wordline and applies a read voltage Vread (e.g., 4.5V) to unselected wordlines. A program voltage, a pass voltage, and a read voltage are higher than a power supply voltage (e.g., 3V). In order to apply a voltage higher than a power supply voltage according to address information, a circuit capable of switching the higher voltage is necessary for the row selection circuit 40. A switch pump scheme or a boosting scheme is used to construct the circuit capable of switching the higher voltage.
A row selection circuit 40 using the switch pump scheme is partially illustrated in FIG. 2.
Referring to FIG. 2, a row selection circuit 40 includes a decoding block 42, a switch pump block 44, and a switch block 46. The decoding block 42 has NAND gates G1 and G2. Address signals DA1-DAi are supplied to the NAND gate G1, and an output signal and a control signal BLKWLdis are supplied to the NAND gate G2. The control signal BLKWLdis is held high during an erase/program/read operation. The switch pump block 44 is coupled to a BLKWL node (or referred to as xe2x80x9cblock wordlinexe2x80x9d), and has a NAND gate G3, a capacitor C1, and NMOS transistors MN1-MN4 that are connected as shown in the figure. The switch block 46 has pass (or transfer) transistors SW1-SW0 each transferring selection signals SS, S15-S0, and GS to their corresponding signal lines SSL, WL15-WL0, and GSL. Gates of the pass transistors SW0-SW17 are commonly coupled to the BLKWL node. The decoding block 42 and the switch pump block 44 constitute a block decoder for selecting a memory block.
When at least one of the address signals DA1-DAi is low, an output signal of the decoding block 42 is made low. In this case, the switch pump block 44 does not perform a pump operation irrespective of a clock signal CLK. On the other hand, when all the address signals DA1-DAi are high, the output signal of the decoding block 42 is made high. In this case, the switch pump block 44 operates based on a low-to-high/high-to-low transition of the clock signal CLK (wherein the low level is a ground voltage level, and the high level is a power supply voltage level). According to the transition of the clock signal CLK, a capacitor C1 repeatedly carries out a charge/discharge operation. If the capacitor C1 is charged by a pumping charge according to the high-to-low transition of the clock signal CLK, the pumping charge is transferred through an NMOS transistor MN1 to increase a voltage of the BLKWL node. When the clock signal CLK then transitions from low to high, a VPP0 voltage (Vread in a read operation, and Vpgm in a program operation) is applied to a gate of the NMOS transistor MN1 through an NMOS transistor MN2 that is shut off by a gate-source voltage difference after predetermined time.
If the capacitor C1 is recharged according to the high-to-low transition of the clock signal CLK, the pumping charge is transferred through the MNOS transistor MN1 to increase a voltage of the BLKWL node. When the clock signal then transition from low to high, the VPP0 voltage is applied to the gate of the NMOS transistor MN1 via the NMOS transistor MN2. As the above procedure is repeated, the voltage of the BLKWL node may be boosted up to xe2x80x9cVPP0+Vtn3xe2x80x9d finally (wherein the xe2x80x9cVtn3xe2x80x9d represents a threshold voltage of an NMOS transistor MN3, and serves to clamp the voltage of the BLKWL node when it is boosted over a required voltage). Therefore, the BLKWL node has a high voltage enough to transfer the program voltage Vpgm/read voltage Vread to a corresponding wordline.
However, a switch pump structure shown in FIG. 2 is not suitable for a low voltage NAND flash memory device. This reason is described below. The clock signal CLK is made low as a power supply voltage is lowered, which means that pumping time required for boosting the voltage of the BLKWL node up to a required voltage becomes elongated. Further, as the pumping operation is carried out, threshold voltages of the NMOS transistors MN1 and MN2 are increased by the body effect. As a result, a voltage level of the BLKWL node is limited by the increased threshold voltage. A row selection circuit using a boosting scheme has been proposed for overcoming disadvantages of the pumping structure.
A circuit diagram of a row selection circuit using a boosting scheme is illustrated in FIG. 3.
Referring to FIG. 3, a row selection circuit 40 includes a decoding block 42xe2x80x2, a precharge block 44xe2x80x2, a switch block 46xe2x80x2, and NMOS transistors MN5, MN10, and MN11. The decoding block 42xe2x80x2 has NAND gates G4, G5, and G6. Address signals DA1-DAi are provided to the NAND gate G4. An output signal of the NAND gate G4 and a control signal XDEXdis are provided to the NAND gate G5. An output signal of the NAND gate G5 and a control signal BLKWLdis are provided to the NAND gate G6. In response to a control signal ERSen, the NMOS transistor MN5 transfers the output signal of the NAND gate G5 to a BLKWL node or shuts off the output signal of the NAND gate G5. The control signal BLKWLdis is held high during an erase/program/read operation, and the control signal XDEXdis is held low while the BLKWL node is precharged.
The precharge block 44xe2x80x2 is coupled to the BLKWL node and includes NMOS transistors MN6-MN9. Current paths of the MNOS transistors MN6-MN9 are serially formed between a VXPSn voltage and the BLKWL node. Control signals VPREi and VPREj are applied to gates of the NMOS transistors MN6 and MN7, respectively. Diode-coupled NMOS transistors MN8 and MN9 are serially connected between a VXPSn voltage and the BLKWL node. An NMOS transistor MN11 is connected between the BLKWL node and a ground voltage and is turned on/off by an output signal of the NAND gate G6. An NMOS transistor MN10 is connected between an SSLGND node and a string selection line SSL and is turned on/off by the output signal of the NAND gate G6.
The switch block 46xe2x80x2 shown in FIG. 3 has the same structure as shown in FIG. 2 and will not be explained in further detail. The decoding block 42xe2x80x2, the precharge block 44xe2x80x2, and the NMOS transistors MN5, MN10, and MN11 constitute a block decoder circuit. The block decoder circuit and the switch block 46xe2x80x2 will repeatedly be present in each memory block so that each memory block may have the same circuit pattern. The SSLGND node has a ground voltage in read and program operations and has a power supply voltage in an erase operation.
When the address signals DA1-DAi applied to the NAND gate G4 are high and the control signal is low, the output signal of the NAND gate G6 is made low. This allows the NMOS transistor MN10 and MN11 to be turned off. Such an operation is performed in a selected memory block. When one of the address signals DA1-DAi applied to the NAND gate G4 is low and the control signal BLKWLdis is high, the output signal of the NAND gate G6 is made high. This allows the NMOS transistors MN10 and MN11 to be turned on. Such an operation is performed in an unselected memory block.
In case of the selected memory block, the BLKWL node is charged to a high voltage VXPSnxe2x88x92Vtn (wherein the xe2x80x9cVtnxe2x80x9d represents a threshold voltage of an NMOS transistor). This is because the NMOS transistor MN10 is being turned off when the signals VPREi and VPREj are activated. In case of the unselected memory block, the BLKWL node has a ground voltage because the NMOS transistor MN10 is being turned on. Then, the signals VPREi and VPREj are activated from a high level of a high voltage to a low level of a ground voltage, and the BLKWL node is floated. If selection signals S0-S15 are made high by a high voltage of one of program, pass, and read voltages, a precharged voltage of the BLKWL node is boosted according to a coupling effect caused by a gate capacitor of pass transistors SW0-SW15. Due to the above procedure, the BLKWL node of the selected memory block is charged to the high voltage while the BLKWL node of the unselected memory block is held at a ground voltage. As a result, high voltages of the selection signals S0-S15 are more easily transferred to their corresponding wordline.
However, the block decoder shown in FIG. 3 suffers from disadvantages as follows. As described above, the precharge voltage of the BKWL node becomes xe2x80x9cVXPSnxe2x88x92Vtnxe2x80x9d in relation with the selected memory block. The threshold voltage xe2x80x9cVtnxe2x80x9d is very high, approximately 3V, because a source voltage is boosted. Particularly, the threshold voltage xe2x80x9cVtnxe2x80x9d is constant irrespective of a change in a power supply voltage, which imposes a heavy burden on performing a boosting operation under a low voltage. This means that the block decoder circuit show in FIG. 3 is not suitable for the low voltage NAND flash memory device.
Also the control signals VPREi and VPREj are coded according to an address. Memory blocks constituting a memory cell array are divided into a plurality of groups. The same control signals are to be provided to each of the groups. Control signals applied to a selected group are activated, while the control signals applied to unselected groups are inactivated. The activated control signals VPREi and VPREj have a high voltage in order to transfer a VXPSn voltage to the BLKWL node. This means that a circuit for applying a high voltage to the activated control signals VPREi and VPREj, i.e., a switch pump circuit is demanded. An example switch pump circuit is disclosed in U.S. Pat. No. 5,861,772 entitled xe2x80x9cCHARGE PUMP CIRCUIT OF NONVOLATILE SEMICONDUCTOR MEMORYxe2x80x9d. As memory blocks constituting a memory cell array increase in number, memory block groups also increase in number. This means increase in number of the control signals that must be applied to memory block groups. Therefore, because more switch pump circuits for applying a high voltage to control signals are demanded, they restrict the layout to increase a chip size. If a high voltage control signal is commonly applied to all blocks without a coding procedure in order to overcome the size restriction, the switch pump circuits see the BLKWL nodes of all the blocks. Thus, a loading capacitor is so large that precharge time becomes longer.
In view of the foregoing, embodiments of the present invention provide a non-volatile memory device having a row selection circuit that is shared by adjacent memory blocks. Further, embodiments of the present invention provide a non-volatile memory device having a row selection circuit capable of being formed with a high integration density.